Via design
In high-speed PCB design, seemingly simple vias often have a great negative impact on circuit design. In order to reduce the adverse effects caused by via parasitics, we can do our best to:
Considering cost and signal quality, a reasonable via size was chosen. For example, for a 6-10 layer memory module PCB design, it is best to choose 10/2OMIL (drill/pad) vias. For some high-density small boards, you can also try using 8/18 mil vias. Under the current technical conditions, it is difficult to use smaller through holes (when the hole depth exceeds 6 times the diameter of the drilled hole, uniform copper plating on the hole wall cannot be guaranteed); Large size to reduce impedance. Using a thinner PCB is beneficial to reduce the two parasitic parameters of the via.
Try not to change the signal routing layer on the PCB, that is, try not to use unnecessary vias.
The pins for power and ground should be pierced nearby. The shorter the lead between the via and the pin, the better.
Place some ground vias close to the signal layer change vias to provide the closest circuit for the signal. It is even possible to place a large number of redundant ground vias on the PCB.
Beta Years of Low Noise and Electromagnetic Interference - Some Experience
If you can use a low-speed chip, you don't need a high-speed chip. High-speed chips are used in critical locations.
—Series resistors can be used to reduce the rate of change of speed at the upper and lower edges of the control circuit.
Try providing some form of damping to the relay, e.g. a closed RC to set the current damping.
Use the lowest frequency clock that meets system requirements.
The clock should be as close as possible to the device using the clock, and the case of the crystal oscillator should be grounded.
Surround the clock region with a ground trace and keep the clock trace as short as possible.
Do not run traces under quartz crystals and noise-sensitive devices.
Keep clock, bus, and chip select signals away from I/O lines and connectors.
A clock line perpendicular to the I/O line has less glitch than a clock line parallel to the /0 line. The I/O drive circuit should be as close to the edge of the PCB as possible, so that it can leave the PCB as soon as possible. The signal entering the PCB should be filtered, and the signal coming from the high-noise area should also be filtered. At the same time, the method of connecting terminal resistors should be used to reduce signal reflection.
The useless end of the MCU should be connected to a high position, or grounded, or defined as an output. The terminals on the IC connected to power and ground should be connected and not empty.
The inputs of unused gates must not be empty, the positive input of unused op amps should be connected to ground, and the negative input should be connected to the output.
Printed boards should use 45 dotted lines instead of 90 dotted lines as much as possible to reduce external transmission and coupling of high-frequency signals.
Printed boards are divided according to frequency and current switching characteristics, and the distance between noise components and non-noise components is greater.
Single-screen and double-sided screens use single-point grounding for power supply and single-point grounding, and the power and ground wires should be as thick as possible.
Analo voltage input lines and reference voltage terminals should be as far away as possible from digital circuit signal lines, especially clocks.
For a/D equipment, the digital part and the analo part must not intersect.
Component pins should be as beans as possible, and decoupling capacitor pins should be as beans as possible.
The key lines should be as thick as possible, and protection areas should be added on both sides. High-speed lines should be short and straight.
Noise-sensitive lines should not run in parallel with high-current and high-speed switching lines.
Do not form current loops around weak signal circuits and low frequency circuits.
Do not loop any signals. If it is unavoidable, the area of the small loop should be located as much as possible. Each integrated circuit has a decoupling capacitor. A small high-frequency bypass capacitor should be added next to each electrolytic capacitor.
Use large-capacity bile capacitors or polycool capacitors instead of electrolytic capacitors as circuits to charge and discharge energy storage capacitors. When using tubular capacitors, the shell should be grounded.
Signal lines that are very sensitive to interference should be grounded, which can effectively suppress crosstalk.
The signal is transmitted on the printed board, and its delay time should not be greater than the nominal delay time of all devices
I will briefly introduce here today, and we will introduce the rest in detail next time!
